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AM79C203资料

2022-04-11 来源：易榕旅网

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Am79213/Am79C203/031

Advanced Subscriber Line Interface Circuit (ASLIC™) DeviceAdvanced Subscriber Line Audio-Processing Circuit(ASLAC™) Device

DISTINCTIVE CHARACTERISTICS

󰀁Performs all of the functions of a codec-filter󰀁Single channel architecture

󰀁Performs Battery-feed, Ring-trip, Signaling, Coding, Hybrid and Test (BORSCHT) functions󰀁Single hardware design meets multiple country requirements through software programming󰀁Standard microprocessor interface

󰀁Industry standard PCM interface with full-time slot assignment󰀁Monitor of two-wire interface voltage and current for subscriber line diagnostics󰀁Low idle power per line󰀁On-hook transmission

󰀁Only battery and +5 V supplies needed󰀁Exceeds LSSGR and CCITT central office requirements󰀁Off-hook and ground-key detectors with programmable thresholds󰀁Programmable line feed characteristics independent of battery voltage󰀁Built-in voice path test modes

󰀁Analog and digital hybrid balance capability󰀁Adaptive hybrid balance capability

󰀁Linear power feed with power management and thermal shutdown features󰀁Abrupt and smooth polarity reversal󰀁Power-cross detection in Ringing and Non-ringing states󰀁Software programmable

—Digital I/O pins

—A-law/µ-law selection

󰀁Linear data available on PCM ports for custom compression and expansion󰀁Compatible with inexpensive protection

networks. Accommodates low tolerance fuse resistors while maintaining longitudinal balance to Bellcore specifications.󰀁Power/Service Denial state󰀁Small physical size

󰀁Integrated ring trip function

󰀁Four relay drivers with built-in energy absorption zener diodes

󰀁Synchronized ring relay operation: zero volts ac on, zero current off󰀁Software enabled Normal or Automatic Ring-Trip state󰀁On-chip 12 kHz and 16 kHz metering generation with on and off meter pulse shaping󰀁Supports loop-start and ground-start signaling󰀁0°C to +70°C commercial operation guaranteed by production testing󰀁–40°C to +85°C temperature range operation available

———————DC loop feed characteristics and current limitLoop supervision detection thresholdsOff-hook detect debounce intervalTwo-wire AC impedanceTranshybrid balance

Transmit and receive gainsEqualization

Publication# 080160 Rev: D Amendment: /0Issue Date: April 2000

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TABLE OF CONTENTS

Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Linecard Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

ASLIC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ASLAC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Connection Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

32-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ASLIC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9ASLAC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ASLIC/ASLAC Devices Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Electrical Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Absolute Maximum Electrical and Thermal Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

ASLIC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16ASLAC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

ASLIC Device Relay Driver Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Input and Output Waveforms for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Master Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Microprocessor Interface (Input Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Microprocessor Interface (Output Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35PCM Highway Timing for XE = 0 (Transmit on Negative PCLK Edge) . . . . . . . . . . . . . . . . . 36PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge) . . . . . . . . . . . . . . . . . 37ASLIC/ASLAC Devices Linecard Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Programmable Filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

General Description of CSD Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Physical Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

PL032 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43PL044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2Am79213/Am79C203/031 Data Sheet

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LIST OF FIGURES

Figure 1.Figure 2.Figure 3.Figure 4.Figure 5.Figure 6.Figure 7.

Transmit and Receive Path Attenuation vs. Frequency . . . . . . . . . . . . . . . . . . .26Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27A-law Gain Linearity with Tone Input (Both Paths). . . . . . . . . . . . . . . . . . . . . . .28µ-law Gain Linearity with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . . .28Total Distortion with Tone Input (Both Paths). . . . . . . . . . . . . . . . . . . . . . . . . . .29A/A Overload Compression. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30ASLIC/ASLAC Typical Linecard Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

LIST OF TABLES

Table 1.Table 2.Table 3.Table 4.Table 5.Table 6.Table 7.Table 8.Table 9.Table 10.Table 11.

Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15ASLIC Device DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17ASLIC Device Relay Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18ASLIC Device Transmission Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .18ASLAC Device DC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20ASLAC Device Transmission and Signaling Specifications . . . . . . . . . . . . . . . .22Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31PCM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32Master Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33User-Programmable Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38ASLIC/ASLAC Devices Linecard Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

ASLIC/ASLAC Products3

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The Am79213/Am79C203/031 Advanced SubscriberLine Interface chip set implements a universal telephoneline interface function. This enables the design of a single,low cost, high performance, fully software programmableline interface card for multiple country applications worldwide. All AC, DC, and signaling parameters are fullyprogrammable via the microprocessor interface.

Additionally, the ASLIC device and ASLAC device haveintegrated self test and line test capabilities to resolvefaults to the line or line circuit. The integrated testcapability is crucial for remote applications wherededicated test hardware is not cost effective. TheTechnical Reference, PID 21325A is recommended to beused with this document.

LINECARD BLOCK DIAGRAM

Loop VoltageSense Resistors

RFA

RingandTestRelays

B(Ring)

RFB

PCM

Relay Driver Outputs

Ring-FeedResistor

ASLIC Device Operat-ing StateRelay Driver Inputs

ASLIC Device SBBD

TransmitReceive

A(Tip)

DC Feed Control

MeteringLoop Voltage MonitorLoop Current Monitor

ASLAC Device

MPI

MPI and PCM BackplaneRingerSupply

Ringing-CurrentSense Resistors

4Am79213/Am79C203/031 Data Sheet

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ORDERING INFORMATIONASLIC Device

Must order Am79C203 or Am79C2031 with the device below.

Am79213JC

TEMPERATURE RANGE

C = Commercial(0°C to 70°C)*

PACKAGE TYPE

J = 32-pin Plastic Leaded Chip Carrier (PL 032)

DEVICE NUMBER/DESCRIPTIONAm79213

Advanced Subscriber Line Interface Circuit

Valid Combinations

Am79213

Valid Combinations

Valid Combinations list configurations planned tobe supported in volume for this device. Consultthe local Legerity sales office to confirm availabil-ity of specific valid combinations and to check onnewly released combinations.

Note:

* Functionality of the device from 0°C to +70°C is guaranteed by production testing. Performance from –40°C to +85°Cis guaranteed by characterization and periodic sampling of production units.

ASLIC/ASLAC Products5

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ORDERING INFORMATION (continued)ASLAC Device

Must order Am79213 with the device below.

Am79C203/031

TEMPERATURE RANGE

C = Commercial(0°C to 70°C)*

PACKAGE TYPE

J = 32-pin Plastic Leaded Chip Carrier (PL032)

Am79C203 only

J = 44-pin Plastic Leaded Chip Carrier (PL044)

Am79C2031 only

DEVICE NUMBER/DESCRIPTIONAm79C203/031

Advanced Subscriber Line Audio-processing Circuit

Valid Combinations

Am79C203Am79C2031

Valid Combinations

Note:

* Functionality of the device from 0°C to +70°C is guaranteed by production testing. Performance from –40°C to +85°Cis guaranteed by characterization and periodic sampling of production units.

6Am79213/Am79C203/031 Data Sheet

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CONNECTION DIAGRAMSTop View32-Pin PLCC

RY1OUTBGNDVBATVCCBDADSB30

29282726

Am79213

2524232221

1415C1VDC16171819

ISUMVLBIASGNDIDIF20RSNSAHPBHPARSVD BAL1NCVREFVTXIDC

29282726

Am79C203

2524232221

141516

VMVOUTINT17181920

AGNDVREFVINRST4

RY2OUTRY3OUTRINGOUT

TMGQBATC5C4C3C2

5678910111213

3213231

Notes:

1.RSVD = Reserved. Do not connect to this pin.2.NC = No Connect

DGNDMCLKTCSAPCLK4

FSI/O1I/O2DCLKDI/OVCCDCSC2C1

5678910111213

321323130

IABIREFVLBIASVCCAIDIFISUMIRTAIRTBIDC

ASLIC/ASLAC Products

IBATDRADXA7

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CONNECTION DIAGRAMS (continued)Top View44-Pin PLCC

DGNDPCLKRSVD6

FSI/O1I/O2I/O3DCLKDI/OVCCDI/O4CSC2C1

7 891011121314151617

543214443424140

3938373635

IBATIABIREFVLBIASVCCAIDIFISUMIRTAIRTBIDCRSVD

Am79C2031

RSVD343332313029RSVD1819202122232425262728RSVDRSVDAGNDRSVDVOUTVREFVININTRSTVMNote:

RSVD = Reserved. Do not connect to this pin.

8Am79213/Am79C203/031 Data Sheet

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PIN DESCRIPTIONSASLIC Device

Pin NamesAD, BDBAL1BGNDC2–C1C5–C3

TypeOutputInputGndInputInput

Description

A and B Line Drivers. These pins provide the currents to the A and B leads of the sub-scriber loop.

Pre-balance. This pin receives voltages that are added to the VTX output signal. They can be used to cancel out the metering echo in the transmit path.

Battery Ground. This pin connects to the ground return for Central Office or talk

battery.

ASLIC Device Control. These ternary logic input pins control the operating state of the ASLIC device.

Test Relay Control. These are control inputs for the test relay drivers in the ASLIC device. A logic Low turns on the relay driver and activates the relay. C3 controls RY1OUT, C4 controls RY2OUT, and C5 controls RY3OUT.Analog and digital ground return for VCC.

High-Pass Filter Capacitor Connections. These pins connect to CHP, the external high-pass filter capacitor that isolates the DC control loop from the voice transmission path.DC Loop Control Current. The DC loop current control line from the ASLAC device is con-nected to this pin. An internal resistance is provided between the IDC pin and RSN. An external noise filter capacitor should be connected between this pin and VREF.A – B Leg Current. The current at this pin is proportional to the difference of the currents flowing out of the AD pin and into the BD pin of the ASLIC device.

A + B Leg Current. The current at this pin is proportional to the absolute value of the sum of the currents flowing out of the AD pin and into the BD pin of the ASLIC device.Quiet Battery Voltage. The QBAT pin is connected to the substrate.

Relay Drivers. These are open collector, high current relay driver outputs with emitters internally connected to BGND. To absorb the inductive pulse from the relay coils, an in-ternal Zener diode is connected between the collector of each driver and BGND.Receive Summing Node. The metallic current (both AC and DC) between AD and BD is equal to ASLIC device current gain, K1, times the current into this pin. Networks that pro-gram receive gain and two-wire impedance connect to this node. This input is nominally at VREF potential.

Reserved. This is used during Legerity testing. In the application, this pin must be floating.A and B Lead Voltage Sense. These pins sense the voltages on the line side of the fuse resistors at the A and B leads. External sense resistors, RSA and RSB, are required to protect these pins from lightning or power cross conditions.

Thermal Management. A resistor connected from this pin to VBAT reduces the on-chip power dissipation by absorbing excess power from the ASLIC device for short-loop con-ditions.

Battery Voltage. This pin supplies battery voltage to the line drivers.

Power Supply. This is the positive supply for low voltage analog and digital circuits in the ASLIC device.

DC Loop VoltageThe voltage on this output is referenced to VREF and is proportional to the negative absolute value of the DC subscriber loop voltage between A and B. This volt-age is a fraction (β) of the voltage between HPA and HPB. This pin connects to the IAB pin on the ASLAC device through external resistor RAB. A voltage that is significantly more positive than VREF on the VDC pin indicates that the ASLIC device is in thermal shutdown.

GNDHPA, HPBIDC

GndCapacitorInput

IDIFISUMQBATRINGOUT, RY1OUT, RY2OUT, RY3OUTRSN

OutputOutputPowerOutput

Input

RSVDSA, SB

InputInput

TMGThermal

VBATVCCVDC

PowerPowerOutput

ASLIC/ASLAC Products9

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Pin NamesVLBIASVREF

TypeInputInput

Description

Longitudinal Offset Voltage. The input to this pin is the offset reference voltage for the ASLIC device longitudinal control loop.

Analog Reference. This voltage is provided by the ASLAC device and is used by the ASLIC device for internal reference purposes. All analog input and output signals inter-facing to the ASLAC device are referenced to this pin. Nominally set to 2.1 V.

Four-Wire Transmit Signal. The voltage between this pin and VREF is a scaled version of the AC component of the voltage sensed between the SA and SB pins. One end of the two-wire input impedance programming network connects to VTX. The voltage at VTX swings positive and negative about VREF.

VTXOutput

ASLAC Device

Pin NamesAGNDC2–C1

TypeGndOutput

Description

Analog (Quiet) Ground. VREF is referenced to this ground.

ASLIC Device Control. These ternary logic output pins are dedicated to controlling the op-erating state of the ASLIC device. The levels of these outputs are logic High, logic Low, and high impedance.

Chip Select. The chip select input (active Low) enables the device so commands and data can be written to or read from it. If chip select is held Low for 16 or more DCLK cy-cles (independent of MCLK or PCLK), a hardware reset is executed at the time chip se-lect returns to logic 1.

Data Clock. The data clock input shifts data into or out of the microprocessor interface of the ASLAC device. The maximum clock rate is 4.096 MHz.Digital Ground. Digital ground return.

Data Input/Output. Control data is serially written into and read out of the ASLAC device via the DI/O pin, with the most significant bit first. The data clock (DCLK) determines the data rate. DI/O is high impedance except when data is being transmitted from the ASLAC device under control of CS.Receive PCM Data. Receive PCM data is received serially on either the DRA or DRB port, with port selection under user program control. Data is received, most significant bit first, in 8-bit PCM or 16-bit linear 2’s complement bursts every 125 µs at the PCLK rate. The receive port is unaffected by the setting of the SMODE bit. (DRB – 44-pin PLCC only.)

Transmit PCM Data. Transmit PCM data is transmitted serially through either the DXA or DXB port, with port selection under user control. The transmission data output is available every 125 µs and is shifted out, most significant bit first, in 8-bit PCM or 16-bit linear 2’s complement bursts at the PCLK rate. DXA/B are high impedance between bursts and while the device is in the Inactive state.

For signaling register operation on the PCM highway, see the SMODE description. (DXB – 44-pin PLCC only.)

Input

Frame Sync. The frame sync signal is an 8 kHz pulse that identifies the beginning of a frame. The ASLAC device references individual time slots with respect to this input, which must be synchronized to PCLK.

Loop Voltage Sense. The IAB pin is a current summing node referenced to VREF. An ex-ternal resistor (RAB) is connected between this pin and the VDC pin of the ASLIC device, In normal operation, current flows out of this pin. When the ASLIC device is in thermal shutdown, current will be forced into this pin.Battery Voltage Sense. The IBAT pin is a current summing node referenced to AGND and receives a current that is proportional to the system battery voltage. A sense resistor/ca-pacitor network is connected between the QBAT pin of the ASLIC device and the IBAT pin.

Input, Active

Low

DCLKDGNDDI/O

InputGndInput/Output

DRA, DRBInput

DXA, DXBOutput

IABInput

IBATInput

10Am79213/Am79C203/031 Data Sheet

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Pin Names

IDCIDIF

TypeOutputInput

Description

DC Loop Control Current. The IDC output supplies a current to the ASLIC device for pro-portional control of the DC loop current flowing through the subscriber loop.

Longitudinal Sense. IDIF is a current input pin fed by the IDIF pin of the ASLIC device. The current in this pin is used by the ASLAC device for supervisory and diagnostic func-tions. The IDIF pin has an internal input resistance so an external longitudinal noise filter capacitor can be connected.

Interrupt. A logic 0 on this pin indicates one or more of the bits in the signaling register has changed states. An interrupt will be generated when activity is sensed on any signal in the Signaling Register not masked by the Mask Register. Once an unmasked activity is sensed, the INT output will be driven Low and held at that state until cleared. See the description of configuration register 6 for operation.

Control Ports. These control lines are TTL compatible and each can be programmed as an input or an output. When programmed as inputs, they can monitor external, TTL com-patible logic circuits. When programmed as outputs, they can control an external logic de-vice or they can be connected to pin C3, C4, or C5 of the ASLIC device to control test relay drivers RY1OUT, RY2OUT and RY3OUT (I/O3, I/O4, 44-pin PLCC version only). In the Output mode, these pins are controlled by the I/O1, I/O2, I/O3, and I/O4 bits in the Channel Control Register, MPI Command 17.

Current Reference. An external resistor (RREF) connected between this pin and analog ground generates an accurate on-chip reference current. This current is used by the ASLAC device in its DC Feed and loop-supervision circuits.

Ring Trip Sense. These pins are current summing nodes referenced to VREF. They pro-vide terminations for external resistors RSR1 and RSR2, which sense the voltages on both sides of the ringing feed resistor connected to the ring bus. To determine the ring-ing current in the loop, the ASLAC device senses the difference between the currents in these pins.

Metallic Sense. ISUM is a current input pin and is fed by the ISUM pin of the ASLIC de-vice. The absolute value of the current in this pin is used by the ASLAC device for super-visory and diagnostic functions.

Master Clock. The master clock is used to operate the digital signal processor. MCLK can be 2.048 MHz, 4.096 MHz or 8.192 MHz. MCLK may be asynchronous to PCLK. Upon initialization, the MCLK input is disabled and relevant circuitry is driven by a connection to PCLK. The MCLK connection may be reestablished under user control.PCM Clock. The PCM clock determines the rate at which PCM data is serially shifted into or out of the PCM ports. PCLK is an integer multiple of the frame sync frequency. The maximum clock frequency is 8.192 MHz and the minimum clock frequency is 128 kHz for companded data. The minimum clock frequency for linear or companded data plus sig-naling data is 256 kHz. The PCLK clock may be asynchronous to MCLK if the initial con-nection state is disabled under user control.

Reset. A logic 0 on this pin resets the ASLAC device to initial default conditions. It is equivalent to a hardware reset command. A signal less than 100 ns should not cause a reset. To ensure proper reset, the minimum length of a reset pulse is 50 µs.Time Slot Control. The time slot control outputs are open drain (requiring an external pull-up resistor to VCCD) and are normally inactive (high impedance). TSCA is active (Low) when PCM data is present on DXA, and TSCB is active (Low) when PCM data is present on DXB. (TSCB and DRB – 44-pin PLCC only.)

Analog Power Supply. VCCA is internally connected to substrate near the analog I/O section.

Digital Power Supply. VCCD is internally connected to substrate near the digital section.Analog Input. The analog output (VTX) from the ASLIC device is applied to the ASLAC device transmit path input, VIN. The signal is sampled, processed, encoded, and trans-mitted on the PCM Highway.

INTOutput, Active

Low

I/O1, I/O2, I/O3,

I/O4

Input/output

IREFReference

IRTA, IRTBInputs

ISUMInput

MCLKInput

PCLKInput

RSTInput, Active

LowOpen Drain Outputs

TSCA, TSCBVCCAVCCDVIN

PowerPowerInput

ASLIC/ASLAC Products11

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Pin NamesVLBIASVMVOUT

TypeOutputOutputOutput

Description

Longitudinal Reference. VLBIAS is programmed by VOFF and supplies the longitudinal reference voltage for the longitudinal control loop to the ASLIC device.

12/16 kHz Metering Signal. For 12/16 kHz teletax, an internally generated and shaped 12 or 16 kHz sine wave metering pulse is output from this pin.

Analog Output. The voice data from the received PCM channel (timeslot) is digitally pro-cessed and converted to an analog signal which is present on the VOUT pin of the ASLAC device.

Analog Reference. This pin provides a voltage reference to be used as the analog zero level reference on the ASLIC device.

VREFOutput

12Am79213/Am79C203/031 Data Sheet

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ASLIC/ASLAC DEVICES FUNCTIONALDESCRIPTION

The ASLIC/ASLAC devices chip set integrates all func-tions of the subscriber line. The chip set comprises anASLIC device and an ASLAC device. The set providestwo basic functions: 1) the ASLIC device, a high-voltage,bipolar device that drives the subscriber line, maintainslongitudinal balance, and senses line conditions; and 2)the ASLAC device, a low-voltage CMOS device thatcombines CODEC, DC Feed control, and line supervi-sion. A complete schematic of a linecard using theASLIC/ASLAC devices chip set is shown in the Figure 7.The ASLIC device uses reliable, bipolar technology toprovide the power necessary to drive a wide variety ofsubscriber lines. It can be programmed by the ASLACdevice to operate in eight different states that controlPower Consumption and Signaling states. This enablesfull control over the subscriber loop. The ASLIC deviceis customized to be used exclusively with the ASLACdevice, providing a two-chip universal line interface. TheASLIC device requires only a +5 V power supply and anegative battery supply for its operation.

The ASLIC device implements a linear loop currentfeeding method with the enhancement of thermal man-agement to limit the amount of power dissipated on theASLIC device by dissipating excess power in an externalresistor.

The ASLAC device is a high-performance, CMOS CO-DEC/filter device with additional digital filters and cir-cuits that allow software control of transmission, DCFeed, and supervision.

Advanced CMOS technology makes the ASLAC devicean economical device that has both the functionality andthe low power consumption required by linecard design-ers to maximize linecard density at minimum cost.When used with an ASLIC device, the ASLAC deviceprovides a complete software-configurable solution tolinecard functions. In addition, the ASLIC/ASLAC devic-es chip set provides system-level solutions for loop su-pervisory functions and metering. In total, the ASLIC/ASLAC devices chip set provides a programmable so-lution that can satisfy worldwide linecard requirementsby software configuration.

All software-programmed coefficients and DC Feed pa-rameters are easily calculated with the AmSLAC3ä soft-ware. This software is provided free of charge and runson an IBM-compatible PC. It allows the designer to entera description of system requirements, then the softwarereturns the necessary coefficients and the predictedsystem response.

The ASLAC device uses the industry standard micro-processor (MPI) and PCM interfaces to communicatewith the system and for interfacing to the 64 kilobit persecond voice network.

The ASLIC device interface unit inside the ASLAC deviceprocesses information regarding line voltages, loop cur-rents, and battery voltage levels. These inputs allow theASLAC device to place several key ASLIC device perfor-mance parameters under programmable supervision.The main functions that can be observed and/or controlledthrough the ASLAC device control interface are:󰀁DC Feed characteristics󰀁Ground-key detection󰀁Off-hook detection󰀁Metering signal

󰀁Longitudinal operating point󰀁Subscriber line voltage and currents󰀁Ring trip

󰀁Abrupt and smooth battery polarity reversal

To accomplish these functions, the ASLAC device col-lects the following information from the ASLIC deviceand the Central Office system:

󰀁The sum and difference of the currents in each loopleg, ISUM, and IDIF󰀁Currents proportional to the:

—voltage across the loop (IAB)—battery voltage (IBAT)

—ringing current in the loop (IRTA – IRTB)The outputs supplied by the ASLAC device are then:󰀁A current proportional to the desired DC loop cur-rent (IDC)󰀁A voltage proportional to the desired longitudinal off-set voltage (VLBIAS)󰀁A 12/16 kHz metering signal (appears on VM for12/16 kHz teletax)

The ASLAC device performs the CODEC and filter func-tions associated with the four-wire section of the sub-scriber line circuitry in a digital switch. These functionsinvolve converting an analog voice signal into digitalPCM samples and converting digital PCM samples backinto an analog signal. During conversion, digital filtersare used to band-limit the voice signals.

The user-programmable filters set the receive andtransmit gain, perform the transhybrid balancing func-tion, permit adjustment of the two-wire termination im-pedance, and provide frequency response adjustment(equalization) of the receive and transmit paths. Adap-tive transhybrid balancing is also included.

ASLIC/ASLAC Products13

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The PCM data can be either 8-bit companded A-lawcode, 8-bit companded µ-law code, or 16-bit linearcode. Voice data is transmitted and received via thePCM highway; control information is written to and readfrom the ASLAC/ASLIC devices chip set over the mi-croprocessor interface.

Besides the CODEC functions, the ASLAC device pro-vides all the sensing, feedback, and clocking neces-sary to completely control ASLIC device functions withprogrammable parameters. The line status is continu-ously available in the ASLAC Device Signaling Regis-ter, which is continuously available via the MPIinterface, or on the PCM highway via a user-program-mable mode. A programmable interrupt provides add-ed flexibility in monitoring line status. System-levelparameters under programmable control include ac-tive and disable loop-current limits, feed resistance,and apparent battery-feed voltage. The longitudinaloperating point is programmable to optimize the ASLICdevice signal swing capability.

The ASLAC device provides signals at 12 or 16 kHz formetering functions. The frequency and level of thesesignals are programmable.

The ASLAC device provides extensive loop supervisioncapability, including off-hook, ring-trip, and ground-keydetection. Detection thresholds for these functions areprogrammable. A programmable debounce timer isavailable that eliminates false detection due to contactbounce. For subscriber line diagnostics, AC and DC lineconditions can be monitored using special test modes.Results are read using the MPI commands.

14Am79213/Am79C203/031 Data Sheet

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ELECTRICAL REQUIREMENTSPower Dissipation

Loop resistance = 0 to ∞ (not including fuse resistors),2 x 50 Ω fuse resistors, VBAT = QBAT = –48 V, VCC =+5 V. For power dissipation measurements, DC Feedconditions are programmed as follows:VAPP (apparent voltage) = 50.2 VILA (Active state current limit) = 42.3 mAILD (Disable state current limit) = 21.2 mARFD (feed resistance) = 807 Ω

Description

ASLIC device power dissipationNormal polarity

VAS (anti-sat activate voltage) = 8.2 VN2 (anti-sat feed resistance factor) = 2VOFF (longitudinal offset voltage) = 6 VRTMG (thermal management resistor) = 1200 ΩRREF (reference current setting resistor) = 7.87 kΩ

Table 1. Power Dissipation

Test Conditions

On-hook DisconnectOn-hook StandbyOn-hook DisableOn-hook Active

Off-hook Active RL = 294 ΩOff-hook Disable RL = 600 Ω

Min

Typ305012033085080085229523

Max7010521545012009501102512026

mWUnit

ASLAC device power dissipation MCLK, PCLK = 2.048 MHz

ASLAC device activated

ASLAC device inactive, MPI Standby state command issuedASLAC device activated

ASLAC device inactive, MPI Standby state command issued

ASLAC device power dissipation MCLK, PCLK > 2.048 MHz

Thermal Resistance

The junction-to-air thermal resistance of the ASLIC de-vice in a 32-pin PLCC package will be less than 45°C/W.The junction-to-air thermal resistance of the ASLAC de-vice in a 32-pin PLCC package will be less than 45°C/W.The junction-to-air thermal resistance of the ASLAC de-vice in a 44-pin PLCC package will be less than 44°C/W.

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ABSOLUTE MAXIMUM ELECTRICALAND THERMAL RATINGSASLIC Device

Storage temperature...................–55°C ≤ TA ≤ +150°CAmbient temperature,

under bias................................–40°C ≤ TA ≤ +85°CAmbient relative humidity

(noncondensing)..................................5% to 100%VCC with respect to AGND/DGND.........–0.4 V to +7 VVBAT, QBAT with respect to BGND.......+0.4 V to –75 VVCC with respect to VBAT, QBAT.........................+80 VBGND with respect to

AGND/DGND................................–0.5 V to +0.5 VVoltage on relay outputs.......................................+7 VAD or BD to BGND:

Continuous........................................–75 V to +1 V10 ms (f = 0.1 Hz)..............................–75 V to +5 V1 µs (f = 0.1 Hz)...............................–90 V to +10 V250 ns (f = 0.1 Hz).........................–120 V to +15 VCurrent into SA or SB: 10 µs rise to Ipeak;1000 µs fall to 0.5 Ipeak;

2000 µs fall to I = 0..........................Ipeak = ±5 mACurrent into SA or SB: 2 µs rise to Ipeak;10 µs fall to 0.5 Ipeak;

20 µs fall to I = 0.........................Ipeak = ±12.5 mACurrent through AD or BD.............................±150 mAC5–C1

to DGND or AGND...............–0.4 V to VCC + 0.4 VMaximum power dissipation, TA = 70°C...........1.67 W

Note: Thermal limiting circuitry on chip will shut down the cir-cuit at a junction temperature of about 160°C. The deviceshould never be exposed to this temperature. Operationabove 145°C junction temperature may degrade device reli-ability. See the SLIC Packaging Considerations for more in-formation.

ASLAC Device

Storage temperature..................–60°C ≤ TA ≤ +125°CAmbient temperature,

under bias...............................–40°C ≤ TA ≤ +85°CAmbient relative humidity

(noncondensing)..................................5% to 100%VCCA, VCCD with respect to DGND.......–0.4 V to +6 VVCCA with respect to VCCD.................................±0.4 VVIN with respect to DGND........–0.4 V to VCCA + 0.4 VAGND.....................................................DGND ±0.4 VLatch up immunity (any pin)...........................±100 mAAny other pin with respect

to DGND...............................–0.4 V to VCC + 0.4 V

Stresses above those listed under Absolute Maximum Ratingsmay cause permanent device failure. Functionality at or abovethese limits is not implied. Exposure to Absolute Maximum Rat-ings for extended periods may affect device reliability.

OPERATING RANGESEnvironmental

Ambient temperature.........0°C to +70°C Commercial*Ambient relative humidity..........................15% to 85%ASLIC Device

VCC..............................................................+5 V ± 5%VBAT, QBAT............................................–18 V to –70 VBGND with respect to GND.......–100 mV to +100 mV Load resistance on VTX to ground...............10 kΩ minASLAC Device

Supplies VCCA, VCCD...................................+5 V ± 5%DGND.....................................................................0 VAGND..................................................DGND ± 50 mV

Operating ranges define those limits over which the function-ality of the device is guaranteed by production testing.* Functionality of the device from 0°C to +70°C is guaranteedby production testing. Performance from –40°C to +85°C isguaranteed by characterization and periodic sampling of pro-duction units.

16Am79213/Am79C203/031 Data Sheet

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PERFORMANCE SPECIFICATIONS

(See note 1) TA = 0°C to 70°C unless otherwise noted.

Table 2. ASLIC Device DC Specifications

No.1

Item

2-wire loop voltage

Condition

Standby state, RL = 1 MΩActive state, RLAD–BD = 600 ΩIRSN = 140 µA

Disable state, RLAD–BD = 600 ΩIRSN = 80 µA

Feed resistance per leg at pins AD and BDISUM currentIDIF current

Standby state

Standby state, RL = 1930 ΩStandby stateA to QBATB to ground

MinQBAT – 1.819.5111.34130 44.635.443.4

TypQBAT – 1.121.112.1925056

MaxQBAT – 0.522.68

13.04375

µAΩUnit

Note4

Ternary input voltage boundaries for C2–C1 pins. Mid-level input source must be high impedance or 3-stateLow boundaryHigh boundaryLogic inputs C2–C1Input High currentInput Low current3-state voltage

IC1 = IC2 = 1 µA

0.82.0

0.8

–200–400

BAL1 pin openIREF = ±1 mA

Tj < 145°C, VDC is referenced to VREF, 35.7 kΩ resistor con-nected from VDC to VREF.VSA – VSB = 40 V.IVDC = 20 µA

4.25.5820

VLBIAS = 3 V

VCC – 0.46.033.3

6.42

VV/VkΩ

–502.0

2.1

4040+502.2

µAmVV

VCC – 1

–8090

200

µA

2003.5

0.8

Logic inputs C5–C3Input High voltageInput Low voltageInput High currentInput Low current

6 VTX output offset78

VREF input voltageβ, Ratio of VDC to loop voltage:

VDC–VREF β=------------------------------------VSA–VSB9

Thermal shutdown

threshold voltage output on VDC

Gain from VLBIAS pin to AD or BD pinInput resistance to AGND, VLBIAS pin

0.02530.0242 0.0232V/V

1011

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Table 2. ASLIC Device DC Specifications (continued)

No.12131415161718

Item

ISUM/ILOOPIDIF/ILONGInput current,SA and SB pinsInput current

HPA and HPB pinsIDC input impedanceK1

Metallic offset current

Incremental DC current gain

1.26

Condition

ILOOP = 10 mAILONG = 10 mA

Min1/3331/667

Typ1/3001/60010.11.82540

–0.4Max1/2731/546333

µA

Unit

Note

kΩA/AmA

ASLIC Device Relay Driver Schematic

RINGOUT RY1OUT RY2OUT RY3OUT

BGND

Table 3. ASLIC Device Relay Driver Specifications

Item

Condition

25 mA per relay sink

On voltage

1 relay on4 relays on

40 mA per relay sink

1 relay on4 relays on

Off leakage, each relay driver

VOH = +6 V

0 Min

Typ0.2250.40.450.8

Max0.30.50.71.0100

µAV

Unit

Note

Table 4. ASLIC Device Transmission Specifications

No.12345

Item

RSN input impedanceVTX output impedanceGain, BAL1 to VTXBAL1 input impedanceInput impedanceA or B to GND

1.43.17

Condition

f = 300 Hz to 3400 Hz

Min

Typ131.5570

1.67.5135Max

UnitΩV/VkΩΩ

4Note4

18Am79213/Am79C203/031 Data Sheet

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Table 4. ASLIC Device Transmission Specifications (continued)

No.678

Item

2- to 4-wire gain

2- to 4-wire gain variation with frequency

2- to 4-wire gain tracking

Condition

–10 dBm, 1 kHz

TA = –40°C to 0°C/70°C to 85°C300 to 3400 Hz relative to 1 kHzTA = –40°C to 0°C/70°C to 85°C+3 dBm to –55 dBm Reference: –10 dBm

TA = –40°C to 0°C/70°C to 85°C–10 dBm, 1 kHz

TA = –40°C to 0°C/70°C to 85°C300 to 3400 Hz relative to 1 kHzTA = –40°C to 0°C/70°C to 85°C+3 dBm to –55 dBm Reference: –10 dBm300 Hz to 3400 Hz0 dBm+4 dBm–12 dBm–8 dBm

VLBIAS = 2.4 V, ILOOP = 30 mA,

VBAT = QBAT = –60 V, DC LOAD = 200 Ω, Load at 16 kHz = 10 kΩActive and Disable states2-wire

TA = –40°C to 0°C/70°C to 85°C4-wire

Psophometricweighted

2-wire

TA = –40°C to 0°C/70°C to 85°C4-wire

Longitudinal balance(IEEE method)Normal polarity

L - T200 to 1000 HzTA = –40°C to 0°C/70°C to 85°C

1000 to 3400 Hz

TA = –40°C to 0°C/70°C to 85°CT - L

200 to 3400 Hz

5853534840

50482525

4540

3, 544, 8

212

42 +7–5–83–956358

–79–75+11+15

dBrnC

Min–12.19–12.24–0.1–0.15–0.1–0.15–0.15–0.20–0.1–0.15–0.1–0.15

Total harmonic distortion2-wire4-wire

2-wire metering overload level13

Idle channel noiseC-message weighted

0Typ–12.04

Max–11.89–11.84+0.1+0.15+0.1+0.15+0.15+0.20+0.1+0.15+0.1+0.15–50–40–50–40

Vp-p

dBUnit

Note

91011

4- to 2-wire gain

4- to 2-wire gain variation with frequency

4- to 2-wire gain tracking

dBmp

L - T, IL = 050 to 3400 Hz

Reverse polarity15

PSRR (VBAT, QBAT)

L - T200 to 1000 HzTA = –40°C to 0°C/70°C to 85°C50 to 3400 Hz3.4 kHz to 50 kHz

ASLIC device in Anti-Sat state(loop open)

f = 50 Hz, CB = 100 nF

f = 200 to 3400 Hz, CB = 100 nF

ASLIC/ASLAC Products19

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Table 4. ASLIC Device Transmission Specifications (continued)

No.16

Item

PSRR (VCC)

50 to 3400 Hz3.4 kHz to 50 kHz

1718

Low frequency induction(REA method)

Longitudinal AC current per wire

Active state, VLONG = 30 Vrms, IL = 20 mA, f = 60 Hz f = 15 to 60 Hz

Condition

Min2525

Typ4535

+23Max

UnitdBdBrnCmArms

4Note3, 52, 4

Table 5. ASLAC Device DC Specifications

No.12345

Item

Input Low voltageInput High voltageInput leakage currentInput hysteresis (FS and RST only)Ternary output voltages C2–C1High voltageLow voltageOutput current6

Output Low voltage on digital outputs

DXA, DXB, DI/O, TNT, TSCA, TSCB, I/O1, I/O2, I/O3, I/O4TSCA, TSCBI/O1, I/O2, I/O3, I/O47

Output High voltage (all digital outputs except INT in the Open Drain state and TSC)DC Feed

IOUT = ±200 µAIOUT = ±200 µAMid levelIOL = 2 mA

–1VCC – 0.85

0.65+10.4

VµA

Condition

(Any digital input)(Any digital input)(Any digital input)

Min–0.52.0–10

0.5Typ

Max0.8VCC + 0.5+10

UnitVµAV

154Note

IOL = 14 mAIOL = 10 mA

0.41.0

IOH = 400 µAVCC – 0.4

ILA = 47.6 mA, RFD = 403 Ω,N2 = 2, VAS = 10.3 V,IBAT = 69.9 µA

Active state,

Normal polarity, IAB = 0, VAPP = 50.2 VIn resistive-feed regionIBAT = 69.9 µA

Adjust IAB until IDC = 0Programmed VAPP = 50.2 VProgrammed VAS = 10.3 V

172.7

188.5

204.9

µA

IDC

∆IAB--------------∆IDCIAB

Measured VAPPMeasured VAS

0.062427.93

0.069429.93±2.2±1.6

0.076431.93

A/AµA

20Am79213/Am79C203/031 Data Sheet

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Table 5. ASLAC Device DC Specifications (continued)

No.9

Item

IDC error among programmed ILA, ILD

Condition

Any ILA or ILD programmedvalue > 20 mA (IDC > 78.7 µA)Any ILA or ILD programmedvalue ≤ 20 mA (IDC ≤ 78.7 µA)

1011

Offset voltage allowedon VIN

VOUT offset voltage

AISN offAISN on

121314

Output voltage, VREFCapacitance load on VREF or VOUTOutput current VOUT

Source or sink

–18.84

Source current < 250 µA or sink current < 25 µAFor VLBIAS equation seelongitudinal control loop

+1–5

13.6

Load current = 0 to 1 mASource or sink

–50–40–802.0

2.1

Min

Typ±5±4

+50+40+802.2200+118.36+2.4+5120400

VpF

mAkΩV%

618

Max

Unit%µA

Note4, 19191010, 191019

15 Input resistance

IDIF pin to VREF16171819

VLBIAS operatingvoltage

Percent error of VLBIAS voltage

Capacitance load onVLBIAS

Capacitance load on IRTA or IRTB

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Table 6. ASLAC Device Transmission and Signaling Specifications

No.1

Item

Insertion loss

Condition

Input: 1014 Hz, –10 dBm0

RG = AR = AX = GR = GX = 0 dB, AISN, R, X, B, and Z filters disabledTA = 0°C to 70°C

TA = –40°C to 0°C/70°C to 85°CTA = 0°C to 70°C

TA = –40°C to 0°C/70°C to 85°CTA = 70°C

TA = 0°C –70°C; VCC = 4.75 – 5.25 VTA = –40°C to 0°C/70°C to 85°CA-D

AX + GX

Min

Typ

Max

Unit Note

A-DD-AA-D + D-A

–0.25

–0.30–0.25–0.30–0.20–0.25–0.34–0.1

0000000+0.25+0.30+0.25+0.30+0.20+0.25+0.34+0.1

Level set error (error be-tween setting andactual value)

D-A

DR to DX gain in FullDigital Loopback mode

AR + GR–0.1–0.3–0.35

+0.1+0.3+0.4

DR input: 1014 Hz, –10 dBm0

RG = AR = AX = GR = GX = 0 dB, AISN, R, X, B, and Z filters disabledTA = –40°C to 0°C/70°C to 85°CAX = 0 dBAR = 0 dBA-D (PCM output)D-A (VOUT)

Idle channel noise,

psophometric weighted (A-law)

dBm0p

–68–78

Idle channel noise,C-message weighted (µ-law)

AX = 0 dBAR = 0 dBA-D (PCM output),D-A (2 wire),

GX = +8 dBGR = –8 dB

–5

+16+12+50.10.30.1

dBrnC0

6789

Coder offset decision value, XnGX step sizeGR step sizePSRR (VCC)Image frequency

A-D, Input signal = 0 V, A-law0 ≤ GX < 10 dB10 ≤ GX ≤ 12 dB–12 ≤ GR ≤ 0 dB

Input: 4800 to 7800 Hz200 mV p-p

Measure 8000 Hz input frequencyA-DD-A

Bits6

dB4

3737

590655

dB4

Group delay

PCLK ≥ 1.53 MHzPCLK ≤ 1.03 MHz

1014 Hz; –10 dBm0

B, X, R, and Z filters set to default

µs4,14

22Am79213/Am79C203/031 Data Sheet

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Table 6. ASLAC Device Transmission and Signaling Specifications (continued)

No.11

Item

Switchhook thresholdsSwitchhook hysteresis12

Ground-key thresholdsGround-key hysteresis1314

Voltage that setsthermal shutdown bitIDIF fault-currentthresholdsFT, pkFT

FT, pkFT hysteresis15

AISN gain accuracy

GAISN = ±0.0625GAISN = ±0.125GAISN = ±0.1875

GAISN = ≤ –0.25 or GAISN ≥ +0.25

1617181920

Metering voltage(MTRA) accuracyMetering voltage noiseRing-trip accuracyRing-trip hysteresisPower-cross accuracy

VZXIZX

During transmissionDuring ringing

–10–10

Measured at ASLAC device VM pinWide-band signal to noise

–16–8–6–4–740–5

+10+10

17, 20

All TGK settingsAll TGK settings

Voltage on ASLIC device VDC withRAB = 35.7 kΩ

Tip-to-battery fault current(mA)19.3, 50.6

–10

+16+8+6+4+7

dB%VµA

4,17,204, 17

+4.19

Condition

All TSH settingsAll TSH settings

–0.90or–10

–10

Min–0.45or–10

–10

+0.90or+10

Typ

Max+0.45or+10

UnitmA%%mA%%

9, 16,

199, 16, 194Note

+10

16, 19

Notes:

1.Unless otherwise specified, test conditions are:

VCC = 5 V, RTMG = 1200 Ω, QBAT = BAT = –51 V, RAB = 35.7 kΩ, RBAT1 = RBAT2 = 365 kΩ, RREF = 7.87 kΩ, RRX = 75 kΩ, RL = 600 Ω, RSA = RSB = 200 kΩ, CHP = 220 nF, CDC1 = 1.0 µF, 50 Ω fuse resistors, RSR1 = RSR2 = 750 kΩ,CAD = CBD = 22 nF, CB = 100 nF and the following network is connected between VTX and RSN:

RT1 18.75 K

VTX

CT 430 pF RT2 18.75 K

RSN

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Ambient temperature = 70°C

Active state, normal polarity for transmission performance0 dBm = 1 mW @ 600 Ω (0.775 Vrms)Programmed DC Feed conditions:

VAPP (apparent battery voltage) = 50.2 VILA (Active state loop-current limit) = 47.6 mAILD (Disable state loop-current limit) = 21.2 mARFD (DC Feed resistance) = 403 ΩVAS (anti-sat activate voltage) = 10.3 VN2 (anti-sat feed resistance factor) = 2VOFF (longitudinal offset voltage) = 8.4 VRG = GX = GR = AX = AR = 0 dBR, X, B, and Z filters set to defaultAISN = 0TSH < ILD

TSH = Programmed switchhook detect threshold currentILD = Programmed disable limit current

DC Feed conditions are normally set by the ASLAC device. When the ASLIC device is tested by itself, its operating conditions must be simulated as if it were connected to an ideal ASLAC device. When the ASLAC device is tested by itself, its operating conditions must simulate as if it were connected to an ideal ASLIC device.2.These tests are performed with the following load impedances:

Frequency < 12 kHz - longitudinal impedance = 500 Ω; metallic impedance = 300 ΩFrequency > 12 kHz - longitudinal impedance = 90 Ω; metallic impedance = 135 Ω

3.This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.4.Not tested or partially tested in production. This parameter is guaranteed by characterization or correlation to other tests.5.When the ASLIC/ASLAC devices are in the anti-sat operating region, this parameter will be degraded. The exact degradation

will depend on system design.6.Guaranteed by design.

7.Overall 1.014 kHz insertion loss error of the ASLIC/ASLAC devices kit is guaranteed to be ≤ 0.34 dB.

8.These VBAT/QBAT, PSRR specifications are valid only when the ASLIC device is used with the ASLAC device that generates

the anti-sat reference. Since the anti-sat reference depends upon the battery voltage sensed by the IBAT pin of the ASLAC device, the PSRR of the kit will depend upon the amount of battery filtering provided by CB.9.Must meet at least one of these specifications.10.These voltages are referred to VREF.

11.These limits refer to the two-wire output of an ideal ASLIC device but reflect only the capabilities of the ASLAC device.12.When relative levels (dBm0) are used, the specification holds for any setting of (AX + GX) gain from 0 to 12 dB or

(AR + GR + RG) from 0 to –12 dB.13.This parameter tested by inclusion in another test.

14.The group delay specification is defined as the sum of the minimum values of the group delays for the transmit and the receive

paths when the transmit and receive time slots are identical and the B, X, R, and Z filters are disabled with null coefficients. For PCLK frequencies between 1.03 MHz and 1.53 MHz, the group delay may vary from one cycle to the next. See also Figure 2, Group Delay Distortion.15.I/O1 and I/O2 have an additional circuit that pulls the pin High during 3-state.16.These limits reflect only the capabilities of the ASLAC device.17.RSR1 = RSR2 = 750 kΩ, RGFD1 = 510 Ω.

18.DC Feed performance derates by 5% when operating from –40°C to 0°C and 70°C to 85°C.19.Threshold values derate by 5% when operating from –40°C to 0°C and 70°C to 85°C.

20.Power cross and ring trip values derate by 5% when operating from –40°C to 0°C and 70°C to 85°C.

24Am79213/Am79C203/031 Data Sheet

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In the following section, the transmit path is defined as the section between the analog input to the ASLAC device(VIN) and the PCM voice output of the ASLAC device A-law/µ-law speech compressor (shown in the technical overviewdocument). The receive path is defined as the section between the PCM voice input to the ASLAC device speechexpander and the analog output of the ASLAC device (VOUT). All limits defined in this section are tested with B = 0,Z = 0 and X = R = RG = 1.

When RG is enabled, a nominal gain of –6.02 dB is added to the digital section of the receive path.When AR is enabled, a nominal gain of –6.02 dB is added to the analog section of the receive path.When AX is enabled, a nominal gain of +6.02 dB is added to the analog section of the transmit path.

When the gains in the transmit path are set to AX = 0 dB and GX = 0 dB, a 1014 Hz sine wave with a nominal voltageof 0.596 Vrms for µ-law and 0.6 Vrms for A-law at the ASLAC device analog input will correspond to a level of 0dBm0 at the PCM voice output. Under these conditions, the overload level of the transmit path is 1.25 Vpeak referencedto VREF.

When the gains in the receive path are set to AR = GR = 0 dB, a 1014 Hz sine wave with a level of 0 dBm0 at thePCM voice input will correspond to a nominal voltage of 0.596 Vrms for µ-law and 0.6 Vrms for A-law at the analogoutput of the ASLAC device. Under these conditions, the maximum receive output level is 1.25 Vpeak referencedtoVREF.

When relative levels (dBm0) are used in any of the following transmission characteristics, the specification holds forany setting of (AX + GX) gain from 0 to 12 dB or (AR + GR + RG) from 0 to –12 dB.These transmission characteristics are valid for 0°C to 70°C and for VCC = +5 V ± 0.25 V.

ASLIC/ASLAC Products25

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Attenuation Distortion

The deviations from nominal attenuation will stay within the limits shown in Figure 1. The reference frequency is 1014Hz and the signal level is –10 dBm0. Minimum transmit attenuation at 60 Hz is 24 dB.

ASLAC Device Specification

10.6

Attenuation (dB)

0.800.65

0.2

0.125

0–0.125

Receive path

0200300600

Frequency (Hz)

300032003400

Figure 1. Transmit and Receive Path Attenuation vs. Frequency

26Am79213/Am79C203/031 Data Sheet

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Group Delay Distortion

For either transmission path, the group delay distortion is within the limits shown in Figure 2. The minimum value ofthe group delay is taken as the reference. The signal level should be –10 dBm0.

420

ASLAC Device Specification

(Either Path)

Delay (µs)

150

05006001000

Frequency (Hz)

26002800

Figure 2. Group Delay Distortion

Single Frequency Distortion

The output signal level at any single frequency in the range of 300 Hz to 3400 Hz, other than that due to an applied0 dBm0 sine wave signal with frequency f0 in the same frequency range, is less than –46 dBm0. With f0 swept between0 to 300 Hz and 3400 Hz to 12 kHz, any generated output signals other than f0 are less than –28 dBm0. Thisspecification is valid for either transmission path.Intermodulation Distortion

Two sine wave signals of different frequencies f1 and f2 (not harmonically related) in the range 300 Hz to 3400 Hzand of equal levels in the range –4 dBm0 to –21 dBm0 will not produce 2 • (f1 – f2) products having a level greaterthan –42 dB relative to the level of the two input signals.

A sine wave signal in the frequency band 300 Hz to 3400 Hz with input level –9 dBm0 and a 50 Hz signal with inputlevel –23 dBm0 will not produce intermodulation products exceeding a level of –56 dBm0. These specifications arevalid for either transmission path.

ASLIC/ASLAC Products27

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Gain Linearity

The gain deviation relative to the gain at –10 dBm0 is within the limits shown in Figure 3 (A-law) and Figure 4 (µ-law) for either transmission path when the input is a sine wave signal of 1014 Hz.

1.5

ASLAC Device Specification

0.550.25

Gain (dB)

–55–50

–40

–10

0+3

Input Level (dBm0)

–0.25–0.55

–1.5

Note:

Relax specification by 0.05 dB at –40°C.

Figure 3. A-law Gain Linearity with Tone Input (Both Paths)

1.4

ASLAC Device Specification

0.450.25

Gain (dB)

–55–50

–37

–10

0+3

Input Level (dBm0)

–0.25–0.45

–1.4

Note:

Relax specification by 0.05 dB at –40°C.

Figure 4. µ-law Gain Linearity with Tone Input (Both Paths)

28Am79213/Am79C203/031 Data Sheet

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Total Distortion, Including Quantizing Distortion

The signal-to-total distortion ratio will exceed the limits shown in Figure 5 for either path when the input signal is asine wave signal of frequency 1014 Hz.

Improved distortion at lower levels in LSSGR applications can be obtained by proper selection of the GX and GRranges.

ASLAC Device Specification

A-law µ-law A 35.5 dB 35.5 dB B 35.5 dB 35.5 dB C 30 dB 31 dB D 25 dB 27 dB

Signal-to-Total Distortion (dB)

–45–40–30

Input Level (dBm0)

Figure 5. Total Distortion with Tone Input (Both Paths)

ASLIC/ASLAC Products29

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Overload Compression

Figure 6 shows the acceptable region of operation for input signal levels above the reference input power (0 dBm0).The conditions for this figure are:

(1) 1 dB < transmit path ≤ +12 dB; (2) –12 dB ≤ receive path < –1 dB; (3) digital voice output connected to digitalvoice input; and (4) measurement analog-to-analog.

Fundamental Output Power

(dBm0)

8765432.621

Acceptable Region

Fundamental Input Power (dBm0)

Figure 6. A/A Overload Compression

30Am79213/Am79C203/031 Data Sheet

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SWITCHING CHARACTERISTICSMicroprocessor Interface

Min. and Max. values are valid for all digital outputs with a 100 pF load, except DI/O, DXA, and DXB, which are validwith 150 pF loads.

Table 7. Microprocessor Interface

No.123456789101112131415161718192021

SymboltDCYtDCHtDCLtDCRtDCFtICSStICSHtICSLtICSOtIDStIDHtOLHtOCSStOCSHtOCSLtOCSOtODDtODHtODOFtODCtRST

Data clock period

Data clock High pulse widthData clock Low pulse widthRise time of clockFall time of clock

Chip select setup time, Input modeChip select hold time, Input modeChip select pulse width, Input modeChip select off time, Input modeInput data setup timeInput data hold timeSLIC output latch valid

Chip select setup time, Output modeChip select hold time, Output modeChip select pulse width, Output modeChip select off time, Output modeOutput data turn on delayOutput data hold timeOutput data turn off delayOutput data validReset pulse width

0503

5050

5530300700

8tDCY

1.2

1.9tDCY – 10tDCH – 20

700

8tDCY

Parameter

Min2449797

2525tDCY – 10tDCH – 20

Typ

Max

Unitsnsnsnsnsnsnsnsnsµsnsnsµsnsnsnsµsnsnsnsnsµs

1, 71, 7611Note

ASLIC/ASLAC Products31

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Table 8. PCM Interface

No.222324252627282930313233343536

SymboltPCYtPCHtPCLtPCFtPCRtFSStFSHtFCHtTSDtTSOtDXDtDXHtDXZtDRStDRH

Parameter

PCM clock period

PCM clock High pulse widthPCM clock Low pulse widthFall time of clockRise time of clockFS setup timeFS hold time FS High pulse widthDelay to TSC validDelay to TSC offPCM data output delayPCM data output hold timePCM data output delay to High-ZPCM data input setup timePCM data input hold time

300tPCY5555525 5

8080808080

Min0.1224848

1515tPCY – 35

Typ

Max7.8125

Unitsµsnsnsnsnsnsnsnsnsnsnsnsnsnsns

33, 4555Note2

32Am79213/Am79C203/031 Data Sheet

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Master Clock

For 2.048 MHz ± 100 ppm, 4.096 MHz ± 100 ppm, or 8.192 MHz ± 100 ppm operation:

Table 9. Master Clock

No.37

SymboltMCY

Parameter

Master clock period (2.048 MHz)Master clock period (4.096 MHz)Master clock period (8.192 MHz)

38394041

tMCRtMCFtMCHtMCL

Rise time of clockFall time of clockMCLK High pulse widthMCLK Low pulse width

4848Min.488.23244.11122.05

Typ.488.28244.14122.07

Max.488.33244.17122.091515

Unitsnsnsnsnsnsnsns

Note2

Notes:

1.DCLK may be stopped in the High or Low state indefinitely without loss of information.

2.The PCM clock (PCLK) frequency must be an integer multiple of the frame sync (FS) frequency with an accuracy of 800 ppm

relative to the MCLK frequency. This allowance includes any jitter that may occur between the PCM signals (FS, PCLK) and MCLK. The actual PCLK rate is dependent on the number of channels allocated within a frame. The ASLAC device supports 2 to128 channels. The minimum clock frequency is 128 kHz. A PCLK of 1.544 MHz may be used for standard U.S. transmission systems.3.TSC is delayed from FS by a typical value of N • tPCY, where N is the value stored in the time/clock slot register.4.tTSO is defined as the time at which the output driver turns off. The actual delay time is dependent on the load circuitry.

The maximum load capacitance on TSC is 150 pF and the minimum pullup resistance is 360 Ω.5.There is special circuitry that will prevent high-power dissipation from occurring when the DXA or DXB pins of two ASLAC

devices are tied together and one ASLAC device starts to transmit before the other has gone into a high-impedance state.6.The first data bit is enabled on the falling edge of Chip Select or on the falling edge of DCLK, whichever occurs last. If chip

select is held Low for less than eight clocks, no command or data is accepted. If chip select is held Low for more than eight clocks, the last 8 data bits are used as command or data.7.The ASLAC device requires 40 cycles of the 8 MHz internal clock (5 µs) between SIO operations. If the MPI is being accessed

while the MCLK (or PCLK if in combined clock mode) input is not active, a Chip Select Off time of 20 µs is required.

ASLIC/ASLAC Products33

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SWITCHING WAVEFORMS

Input and Output Waveforms for AC Tests

2.4

2.00.8

}

Test Points

{

2.00.8

0.45

Master Clock Timing

VIH

VIL

34Am79213/Am79C203/031 Data Sheet

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Microprocessor Interface (Input Mode)

125DCLKVIHVILVILVIH3746CS810DINData Valid11Data ValidData Valid129In/Outputs C1, C2, I/O1, I/O2, I/O3*, I/O4** Available on 44-pin version only Data ValidData ValidMicroprocessor Interface (Output Mode)

VIH

DCLK

VIL

1315CS1416201817DOUTThree-State

VOHVOL

Data Valid

Three-State

ASLIC/ASLAC Products35

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PCM Highway Timing for XE = 0 (Transmit on Negative PCLK Edge)

Time Slot ZeroClock Slot Zero

2225

VIH

PCLK

VIL

TSCA/TSCB

See Note 4

VOH

DXA/DXB

First BitVOL

VIH

DRA/DRB

FirstBit

SecondBitVIL

36Am79213/Am79C203/031 Data Sheet

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PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge)

Time Slot ZeroClock Slot Zero

VIH

PCLK

VIL

TSCA/TSCB

See Note 4

VOH

DXA/DXB

First BitVOL

VIH

DRA/DRB

FirstBit

SecondBitVIL

ASLIC/ASLAC Products37

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Table 10. User-Programmable Components

ZT=63.5•(Z2WIN–2RF)

ZT is connected between the VTX and RSN pins. The fuse re-sistors are RF. Z2WIN is the desired 2-wire AC input imped-ance. When computing ZT, the internal current amplifier pole and any external stray capacitance between VTX and RSN must be taken into account.

ZRX is connected from VRX to RSN. ZT is defined above, and G42L is the desired receive gain.

ZRX

ZL254•ZT

=-----------•--------------------------------------------------------G42LZT+63.5•(ZL+2RF)

Thermal Management Equations (Normal Active and Tip Open States)RTMG

VBAT–VOFF=------------------------------------ILOOP

(VBAT–VOFF–(ILOOP•RL))=-----------------------------------------------------------------------------------RTMG

RTMG is connected from TMG to VBAT and is used to reduce power dissipation within the ASLIC device in normal Active and Tip Open states.

Power dissipated in the thermal management resistor, RTMG, during normal Active and Tip Open states

PRTMG

PSLIC=VBAT•ILOOP–PRTMG–RL•(ILOOP)+0.12W

Power dissipated in the ASLIC device while in normal Active and Tip Open states

Thermal Management equations (Polarity Reverse State)

Note: ASLIC device die temperature should not exceed 140°C.PSLIC=VBAT•ILOOP–(RL•(ILOOP))+0.12WTSLIC=PSLIC•θjA+TAMBIENTThetajA(θjA)=43°⁄watt

Power dissipated in the ASLIC device while in the Polarity Reverse stateTotal die temperature

Thermal impedance of the 32-pin plastic leaded chip carrier package

38Am79213/Am79C203/031 Data Sheet

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ASLIC/ASLAC DEVICES LINECARD SCHEMATIC

+5 V

ASLIC(32-Pin PLCC)

VCCGND

VREF

RSA

RFA

K2A

VCC

K1K2K3K4

TESTEBUSS

C.O. BATTERY

CS+3U3142

HPA

CHP

RSB

HPBSB

K2BB

K1B

CBDRFB

K1A

CADAD

IDCRSN

ASLIC

(32-/44-Pin PLCC)

+5 V+5 V

VCCAVCCDAGNDVREF

CDC1

RRX

IDCVOUT

DGND

+U1

RINGOUTRY1OUTRY2OUTRY3OUT

BAL1VTXISUMIDIFVDCVLBIAS

C5C4C3C2C1RSVDNC

BGND

TMG

RTMGCBATQBAT

IBAT

VBAT

RBAT2RBAT1

+CBVREF

CDIFRAB

VMVINISUMIDIFIABVLBIAS*I/O4

*I/O3I/O2I/O1C2C1

DRADXATSCA*DRB*DXB*TSCBFSPCLK MCLKDCLKDI/O

RSTINTCS+(32-/44-Pin PLCC)MPI & PCM Highway

Dual PCM Highway

RGFD1

RSR1

IRTAIRTBIREFRREF

(–) C.O.

BATTERY

RING BUS

RSR2

*These pins are unavailable for 32-pin PLCC option.

Battery Ground

Analog Ground

Digital Ground

Polarized Capacitor

Non polarized Capacitor

+ indicates bias

Notes:

1.This application ckt is valid only to 2.2 V metering.

2.If the RSB sense resistor is moved so that it is exposed to the ringing voltage, see the discussion in the Line Fault

Alarm section.

Figure 7. ASLIC/ASLAC Typical Linecard Schematic

ASLIC/ASLAC Products39

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Table 11. ASLIC/ASLAC Devices Linecard Parts List

ItemU1U2U3D1RFA, RFBRSA, RSBRSR1, RSR2

TypeASLIC deviceASLAC deviceTCM1060DiodeResistorResistorResistor

100 mA50 Ω200 kΩ750 kΩ

2%2%2%

100 V2 W1/4 W1/4 W

Transient Voltage Suppressor, Texas Instruments1N4002

Fusible protection resistorsSense resistors

Matched to within 0.2% for initial tolerance and 0 to 70°C ambient temperature range.17 mW typ

RGFD1RRX*RT*

RBAT1, RBAT2RABRREFRTMG *RM*RTESTCDIFCAD, CBD *CBATCHPCBCDC1CM*CS *K1K2K3, K4

ResistorResistorResistorResistorResistorResistorResistorResistorResistorCapacitorCapacitorCapacitorCapacitorCapacitorCapacitorCapacitorCapacitorRelayRelayRelay

510 Ω51.1 kΩ51.1 kΩ365 kΩ35.7 kΩ7.87 kΩ1600 Ω3.16 kΩ3 kΩ6.8 nF22 nF150 nF220 nF100 nF1.0 µF1.8 nF100 nF5 V coil5 V coil5 V coil

2%1%1%1%1%1%5%1%1%20%10%20%20%20%20%10%20%

2 W1/8 W1/8 W1/8 W1/8 W1/8 W4 W1/8 W5 W5 V100 V100 V100 V100 V5 V5 V100 V≤200 mW≤200 mW≤200 mW

1.2 W typ<1 mW<1mW<5 mW<1 mW<1 mW

Application dependentApplication dependent

Used only if ringing tests are required.Ceramic

Ceramic, not voltage sensitiveCeramic, VBAT Typ.Ceramic, VBAT Typ.Ceramic, 0.5 VBAT TypCeramicCeramic

Protector speed up capacitorDPDT ring relay

DPDT (optional) line circuit testoptional

Value

Tol.

Rating

Comments

Note:

* Value can be adjusted to suit application.

40Am79213/Am79C203/031 Data Sheet

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PROGRAMMABLE FILTERS

General Description of CSD Coefficients

The filter functions are performed by a series of multiplications and accumulations. A multiplication is accomplishedby repeatedly shifting the multiplicand and summing the result with the previous value at that summation node. Themethod used in the ASLAC device is known as Canonic Signed Digit (CSD) multiplication and splits each coefficientinto a series of CSD coefficients.

Each programmable FIR filter section has the following general transfer function:

HF(z)=h0+h1z

–1

–2

–n

+h2z+…+hnz

Equation (1)

where the number of taps in the filter = n + 1.The transfer function for IIR part of Z and B filters is:

1Hl(Z)=---------------------------------–1

1–h(n+1)z

Equation (2)

The values of the user-defined coefficients (hi) are assigned via the MPI. Each of the coefficients (hi) is defined inthe following general equation:

hi=B12

–M1

+B22

–M2

++…+BN2

–MN

Equation (3)

where:

Mi = the number of shifts = Mi ≤ Mi + 1Bi = sign = ±1

N = number of CSD coefficients.

The value of hi in Equation 3 represents a decimal number which is broken down into a sum of successive values of:

±1.0 multiplied by 2–0, or 2–1, or 2–2 … 2–7 …or

±1.0 multiplied by 1, or 1/2, or 1/4 … 1/128 …

The limit on the negative powers of 2 is determined by the length of the registers in the ALU.

The coefficient hi in Equation 3 can be considered to be a value made up of N binary 1s in a binary register wherethe left part represents whole numbers, the right part represents decimal fractions, and a decimal point separatesthem. The first binary 1 is shifted M1 bits to the right of the decimal point; the second binary 1 is shifted M2 bits tothe right of the decimal point; the third binary 1 is shifted M3 bits to the right of the decimal point, and so on.Note that when M1 is 0, the resulting value is a binary 1 in front of the decimal point, that is, no shift. If M2 is also 0,the result is another binary 1 in front of the decimal point, giving a total value of binary 10 in front of the decimal point(i.e., a decimal value of 2.0). The value of N, therefore, determines the range of values the coefficient hi can take(e.g., if N = 3 the maximum and minimum values are ±3, and if N = 4 the values are between ±4).Detailed Description of ASLAC Device Coefficients

The CSD coding scheme in the ASLAC device uses a value called mi, where mi represents the distance shifted rightof the decimal point for the first binary 1. m2 represents the distance shifted to the right of the previous binary 1, andm3 represents the number of shifts to the right of the second binary 1. Note that the range of values determined byN is unchanged. Equation 3 is now modified (in the case of N = 4) to:

hi=B12hi=C12hi=C12

–M1–m1

+B22

–M2

+B32

–M3

+B42

–M4

–(m1+m2+m3)

–m4

–(m1+m2+m3+m4)

Equation (4)

+C1C2C3C42

+C1C22í1+C22î

–(m1+m2)–m2

+C1C2C32

–m3

Equation (5)Equation (6)

–m1ì

[1+C32(1+C42

ü)]ýþ

ASLIC/ASLAC Products41

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where:

M1 = m1M2 = m1+m2M3 = m1+m2+m3M4 = m1+m2+m3+m4

B1 = C1B2 = C1 • C2B3 = C1 • C2 • C3B4 = C1 • C2 • C3 • C4

In the ASLAC device, a coefficient, hi, consists of N CSD coefficients, each being made up of 4 bits and formattedas Cxymxy, where Cxy is one bit (MSB) and mxy is 3 bits. Each CSD coefficient is broken down as follows:

Cxymxy000:001:010:011:100:101:110:111:y

is the sign bit (0 = positive, 1 = negative).

is the 3-bit shift code. It is encoded as a binary number as follows:0 shifts1 shifts2 shifts3 shifts4 shifts5 shifts6 shifts7 shifts

is the coefficient number (the i in hi).

x is the position of this CSD coefficient within the hi coefficient. The most significant binary 1 is represented by x = 1.The next most significant binary 1 is represented by x = 2, and so on.

Thus, C13m13 represents the sign and the relative shift position for the first (most significant) binary 1 in the 4th (h3)coefficient.

The number of CSD coefficients, N, is limited to 4 in the GR, GX, R, X, Z, and the IIR part of the B filter, and 3 forthe FIR part of the B filter. Note also that the GX-filter coefficient equation is slightly different from the other filters.

hiGX=1+hi

Equation (7)

Please refer to the Am79213/Am79C203/031 Technical Reference, PID 21325A detailing the commands for completedetails on programming the coefficients.

42Am79213/Am79C203/031 Data Sheet

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PHYSICAL DIMENSIONPL032

.447.453.485.495.009.015.125.140.080.095SEATINGPLANE.400REF..013.021.026.032TOP VIEW.050 REF.SIDE VIEW.042.056.585.595.547.553Pin 1 I.D..490.53016-038FPO-5PL 032DA796-28-94 aePL044

.685.695.042.056.062.083.650.656Pin 1 I.D..685.695.650.656.500.590REF.630.013.021.026.032.050 REF.009.015.090.120.165.180SEATING PLANETOP VIEWSIDE VIEW16-038-SQPL 044DA786-28-94 aeASLIC/ASLAC Products43

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REVISION SUMMARY

Revision A to Revision B

••••••

Fixed the figure numbering.

Minor changes were made to the data sheet style and format to conform to Legerity standards.The physical dimension (PL032 and PL044) was added to the Physical Dimension section.Updated the Pin Description table to correct inconsistencies.

Minor changes were made to the data sheet style and format to conform to Legerity standards.

Page 26, Attenuation Distortion, The sentence “The attenuation of the signal in either path is nominally inde-pendent of the frequency” was deleted.

Revision B to Revision C

Revision C to Revision D

44Am79213/Am79C203/031 Data Sheet

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Notes:

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Notes:

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Legerity provides silicon solutions that enhance the performance, speeds time-to-market, and lowers the systemcost of our customers' products. By combining process, design, systems architecture, and a complete set of softwareand hardware support tools with unparalleled factory and worldwide field applications support, Legerity ensures itscustomers enjoy a smoother design experience. It is this commitment to our customers that places Legerity in a classby itself.

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The contents of this document are provided in connection with Legerity, Inc. products. Legerity makes no representations or warranties with re-spect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and productdescriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rightsis granted by this publication. Except as set forth in Legerity's Standard Terms and Conditions of Sale, Legerity assumes no liability whatsoever,and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitnessfor a particular purpose, or infringement of any intellectual property right.

Legerity's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into thebody, or in other applications intended to support or sustain life, or in any other application in which the failure of Legerity's product could createa situation where personal injury, death, or severe property or environmental damage may occur. Legerity reserves the right to discontinue ormake changes to its products at any time without notice.

Trademarks

Legerity, the Legerity logo, and combinations thereof, and AmSLAC3, ASLAC, and ASLIC are trademarks of Legerity, Inc.

Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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